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Proceedings Paper

Multi-channel high-speed CMOS image acquisition and pre-processing system
Author(s): Chun-feng Sun; Feng Yuan; Zhen-liang Ding
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Paper Abstract

A new multi-channel high-speed CMOS image acquisition and pre-processing system is designed to realize the image acquisition, data transmission, time sequential control and simple image processing by high-speed CMOS image sensor. The modular structure design, LVDS and ping-pong cache techniques used during the designed image data acquisition sub-system design ensure the real-time data acquisition and transmission. Furthermore, a new histogram equalization algorithm of adaptive threshold value based on the reassignment of redundant gray level is incorporated in the image preprocessing module of FPGA. The iterative method is used in the course of setting threshold value, and a redundant graylevel is redistributed rationally according to the proportional gray level interval. The over-enhancement of background is restrained and the feasibility of mergence of foreground details is reduced. The experimental certificates show that the system can be used to realize the image acquisition, transmission, memory and pre-processing to 590MPixels/s data size, and make for the design and realization of the subsequent system.

Paper Details

Date Published: 12 January 2009
PDF: 6 pages
Proc. SPIE 7133, Fifth International Symposium on Instrumentation Science and Technology, 713322 (12 January 2009); doi: 10.1117/12.810514
Show Author Affiliations
Chun-feng Sun, Harbin Institute of Technology (China)
Feng Yuan, Harbin Institute of Technology (China)
Zhen-liang Ding, Harbin Institute of Technology (China)


Published in SPIE Proceedings Vol. 7133:
Fifth International Symposium on Instrumentation Science and Technology
Jiubin Tan; Xianfang Wen, Editor(s)

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