Share Email Print
cover

Proceedings Paper

Process capability comparison between LELE DPT and spacer for NAND flash 32nm and below
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This work demonstrates a methodology for evaluating the multiple feature error budget of NAND-Flash Gate layer and investigates the process capability of the Double Patterning Technology (DPT) options, LELE and Spacer, for NAND Flash 32nm and below. Since the effective k1 limit for DPT is near 0.14 for dense 1D features, three types of ASML scanners are potential candidates for imaging such devices: XT:1400, XT:1700i and XT:1900i. We will present the results of a simulation evaluation of the DPT process capability of these scanners for NAND-Flash Gate layer with 32nm and 22nm half pitch. The DPT capability involves not only lithography but also the subsequent patterning steps of the selected process flow. Moreover, the pattern sensitivity to scanner parameter variations increases with further scaling. It is therefore crucial to take into account the reasonable budgets of scanner dose, focus and overlay errors as well as the error budgets of film deposition, etch and mask registration. This work will not only evaluate the LELE DPT and Spacer feasibility for the mentioned scanners but also analyze the main contributors of CDU in DPT processes and indicate directions we may follow to improve.

Paper Details

Date Published: 4 December 2008
PDF: 11 pages
Proc. SPIE 7140, Lithography Asia 2008, 714035 (4 December 2008); doi: 10.1117/12.808003
Show Author Affiliations
Shih-en Tseng, ASML (Taiwan)
Alek C. Chen, ASML (Taiwan)


Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

© SPIE. Terms of Use
Back to Top