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Proceedings Paper

Design on DDR caching control with ping-pong operation for high-speed data acquisition system with PCI Express interface
Author(s): Xiaoying Zhu; Yong Zhang; Nan Han
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Paper Abstract

Data caching is an indispensable part of high-speed data acquisition system, and it makes an important effect on coordinating the speed of data transfer and data processing. In the article, a data caching controller with ping-pong operation is designed after discussion on the features of data transmission with PCI Express interface. The controller's structure and principle is described, as well as the control logic. Additionally, the controller shows the idea of pipeline, where the command sending and data transfer control are separated on controlling the DDR controllers. The result indicates that the design could be widely used in the seamless caching and high-speed data process system. System efficiency will be improved, and the logic design will be simplified.

Paper Details

Date Published: 13 October 2008
PDF: 5 pages
Proc. SPIE 7129, Seventh International Symposium on Instrumentation and Control Technology: Optoelectronic Technology and Instruments, Control Theory and Automation, and Space Exploration, 712921 (13 October 2008); doi: 10.1117/12.807448
Show Author Affiliations
Xiaoying Zhu, Beijing Univ. of Aeronautics and Astronautics (China)
Yong Zhang, Beijing Univ. of Aeronautics and Astronautics (China)
Nan Han, Beijing Univ. of Aeronautics and Astronautics (China)


Published in SPIE Proceedings Vol. 7129:
Seventh International Symposium on Instrumentation and Control Technology: Optoelectronic Technology and Instruments, Control Theory and Automation, and Space Exploration

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