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Proceedings Paper

Throughput improvement from routing reduction by using CPE (correction per exposure)
Author(s): Ray C. Chang; Jui-Chin Yang; Chia-Hung Chen; Chi-Chun Lin; Cathy Wang; Wythe Lin; Chia-Chi Chen
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Paper Abstract

The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE). We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.

Paper Details

Date Published: 4 December 2008
PDF: 9 pages
Proc. SPIE 7140, Lithography Asia 2008, 714043 (4 December 2008); doi: 10.1117/12.806643
Show Author Affiliations
Ray C. Chang, Inotera Memories Inc. (Taiwan)
Jui-Chin Yang, Inotera Memories Inc. (Taiwan)
Chia-Hung Chen, Inotera Memories Inc. (Taiwan)
Chi-Chun Lin, Inotera Memories Inc. (Taiwan)
Cathy Wang, ASML Taiwan Ltd. (Taiwan)
Wythe Lin, ASML Taiwan Ltd. (Taiwan)
Chia-Chi Chen, ASML Taiwan Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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