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Proceedings Paper

Simulation and experimental validation of substrate noise reduction techniques for power switching circuits
Author(s): Jian Yang; Hongwei Zhao; Iven Zheng; Tommy Mao; Weiying Li; Richard Wang
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Paper Abstract

Single chip integrated power switching circuits can generate huge substrate noise, which impacts the circuit performance of noise sensitive blocks on the same chip. In this paper, the effects of several schematic and layout techniques to reduce substrate noise, including optimizing gate resistors and capacitors, merging NWELL of power devices, adding PEPI around NWELLs, using separated PADs for less noisy blocks, are validated by both simulation and silicon experiments.

Paper Details

Date Published: 13 October 2008
PDF: 5 pages
Proc. SPIE 7127, Seventh International Symposium on Instrumentation and Control Technology: Sensors and Instruments, Computer Simulation, and Artificial Intelligence, 71271M (13 October 2008); doi: 10.1117/12.806572
Show Author Affiliations
Jian Yang, Freescale Semiconductor (China) Ltd. (China)
Hongwei Zhao, Freescale Semiconductor (China) Ltd. (China)
Iven Zheng, Freescale Semiconductor (China) Ltd. (China)
Tommy Mao, Freescale Semiconductor (China) Ltd. (China)
Weiying Li, Freescale Semiconductor (China) Ltd. (China)
Richard Wang, Freescale Semiconductor (China) Ltd. (China)


Published in SPIE Proceedings Vol. 7127:
Seventh International Symposium on Instrumentation and Control Technology: Sensors and Instruments, Computer Simulation, and Artificial Intelligence

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