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Proceedings Paper

Iris matching with configurable hardware
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Paper Abstract

Iris recognition systems have recently become an attractive identification method because of their extremely high accuracy. Most modern iris recognition systems are currently deployed on traditional sequential digital systems, such as a computer. However, modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. In this study, iris matching, a repeatedly executed portion of a modern iris recognition algorithm is parallelized on an FPGA system. We demonstrate a 19 times speedup of the parallelized algorithm on the FPGA system when compared to a state-of-the-art CPU-based version.

Paper Details

Date Published: 4 February 2009
PDF: 10 pages
Proc. SPIE 7244, Real-Time Image and Video Processing 2009, 724402 (4 February 2009); doi: 10.1117/12.805963
Show Author Affiliations
Ryan N. Rakvic, U.S. Naval Academy (United States)
Randy P. Broussard, U.S. Naval Academy (United States)
Delores Etter, Southern Methodist Univ. (United States)
Lauren Kennell, U.S. Naval Academy (United States)
Jim Matey, U.S. Naval Academy (United States)

Published in SPIE Proceedings Vol. 7244:
Real-Time Image and Video Processing 2009
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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