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Proceedings Paper

Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder
Author(s): Thomas Horvath; Da-ke He
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Paper Abstract

Wyner-Ziv based video codecs reverse the processing complexity between encoders and decoders such that the complexity of the encoder can be significantly reduced at the expense of highly complex decoders requiring hardware accelerators to achieve real time performance. In this paper we describe a flexible hardware architecture for processing the Belief Propagation algorithm in a real time Wyner-Ziv video decoder for several hundred, very large, Low Density Parity Check (LDPC) codes. The proposed architecture features a hierarchical memory structure to provide a caching capability to overcome the high memory bandwidths needed to supply data to the processors. By taking advantage of the deterministic nature of LDPC codes to increase cache utilization, we are able to substantially reduce the size of expensive, high speed memory needed to support the processing of large codes compared to designs implementing a single layer memory structure.

Paper Details

Date Published: 5 February 2009
PDF: 6 pages
Proc. SPIE 7244, Real-Time Image and Video Processing 2009, 724407 (5 February 2009); doi: 10.1117/12.805962
Show Author Affiliations
Thomas Horvath, IBM Thomas J. Watson Research Ctr. (United States)
Da-ke He, IBM Thomas J. Watson Research Ctr. (United States)


Published in SPIE Proceedings Vol. 7244:
Real-Time Image and Video Processing 2009
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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