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Proceedings Paper

Patterning performance of hyper NA immersion lithography for 32nm node logic process
Author(s): Kazuhiro Takahata; Masanari Kajiwara; Yosuke Kitamura; Tomoko Ojima; Masaki Satake; Hiroharu Fujise; Yuriko Seino; Tatsuhiko Ema; Manabu Takakuwa; Shinichiro Nakagawa; Takuya Kono; Masafumi Asano; Suigen Kyo; Akiko Nomachi; Hideaki Harakawa; Tatsuya Ishida; Shunsuke Hasegawa; Katsura Miyashita; Takashi Murakami; Seiji Nagahara; Kazuhiro Takeda; Shoji Mimotogi; Soichi Inoue
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Paper Abstract

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Paper Details

Date Published: 4 December 2008
PDF: 10 pages
Proc. SPIE 7140, Lithography Asia 2008, 714017 (4 December 2008); doi: 10.1117/12.804739
Show Author Affiliations
Kazuhiro Takahata, Toshiba Corp. (Japan)
Masanari Kajiwara, Toshiba Corp. (Japan)
Yosuke Kitamura, Toshiba Corp. (Japan)
Tomoko Ojima, Toshiba Corp. (Japan)
Masaki Satake, Toshiba Corp. (Japan)
Hiroharu Fujise, Toshiba Corp. (Japan)
Yuriko Seino, Toshiba Corp. (Japan)
Tatsuhiko Ema, Toshiba Corp. (Japan)
Manabu Takakuwa, Toshiba Corp. (Japan)
Shinichiro Nakagawa, Toshiba Corp. (Japan)
Takuya Kono, Toshiba Corp. (Japan)
Masafumi Asano, Toshiba Corp. (Japan)
Suigen Kyo, Toshiba Corp. (Japan)
Akiko Nomachi, Toshiba Corp. (Japan)
Hideaki Harakawa, Toshiba Corp. (Japan)
Tatsuya Ishida, Toshiba Corp. (Japan)
Shunsuke Hasegawa, Toshiba Corp. (Japan)
Katsura Miyashita, Toshiba Corp. (Japan)
Takashi Murakami, NEC Electronics Corp. (Japan)
Seiji Nagahara, NEC Electronics Corp. (Japan)
Kazuhiro Takeda, NEC Electronics Corp. (Japan)
Shoji Mimotogi, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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