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Proceedings Paper

Alternative technology for double patterning process simplification
Author(s): Hee-Youl Lim; Kyo-Young Jang; Jae-Heon Kim; Sung-Gu Lee; Sarohan Park; Tae-Hwan Kim; Cheol-Kyu Bok; Seung-Chan Moon
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Paper Abstract

In this paper, we will present experimental results on sub-40nm node patterning of DRAM and some technical issues for capping freezing in simplified double patterning lithography. Lithography resolution limit of single pattern is 40nm in ArF immersion process. For sub-40nm patterning, we have to use double patterning lithography or EUV process. But, double patterning lithography process is very complicated and expensive solution. And EUV volume production technology will be not ready until 2012. Therefore, we have tried a simplified double patterning lithography.

Paper Details

Date Published: 4 December 2008
PDF: 8 pages
Proc. SPIE 7140, Lithography Asia 2008, 714020 (4 December 2008); doi: 10.1117/12.804657
Show Author Affiliations
Hee-Youl Lim, Hynix Semiconductor Inc. (South Korea)
Kyo-Young Jang, Hynix Semiconductor Inc. (South Korea)
Jae-Heon Kim, Hynix Semiconductor Inc. (South Korea)
Sung-Gu Lee, Hynix Semiconductor Inc. (South Korea)
Sarohan Park, Hynix Semiconductor Inc. (South Korea)
Tae-Hwan Kim, Hynix Semiconductor Inc. (South Korea)
Cheol-Kyu Bok, Hynix Semiconductor Inc. (South Korea)
Seung-Chan Moon, Hynix Semiconductor Inc. (South Korea)

Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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