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Proceedings Paper

Resolution enhancement techniques for contact hole printing of sub-50nm memory device
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Paper Abstract

In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size. In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.

Paper Details

Date Published: 4 December 2008
PDF: 7 pages
Proc. SPIE 7140, Lithography Asia 2008, 714034 (4 December 2008); doi: 10.1117/12.804646
Show Author Affiliations
Hye-Jin Shin, Hynix Semiconductor Inc. (South Korea)
Tae-jun You, Hynix Semiconductor Inc. (South Korea)
Min-Ae Yoo, Hynix Semiconductor Inc. (South Korea)
Jin-Young Choi, Hynix Semiconductor Inc. (South Korea)
Kiho Yang, Hynix Semiconductor Inc. (South Korea)
Chan-Ha Park, Hynix Semiconductor Inc. (South Korea)
Dong-gyu Yim, Hynix Semiconductor Inc. (South Korea)

Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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