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Proceedings Paper

32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography
Author(s): Robert T. Greenway; Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park; John S. Petersen
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Paper Abstract

As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

Paper Details

Date Published: 17 October 2008
PDF: 12 pages
Proc. SPIE 7122, Photomask Technology 2008, 71221L (17 October 2008); doi: 10.1117/12.801883
Show Author Affiliations
Robert T. Greenway, Petersen Advanced Lithography (United States)
Kwangok Jeong, Univ. of California, San Diego (United States)
Andrew B. Kahng, Univ. of California, San Diego (United States)
Chul-Hong Park, Univ. of California, San Diego (United States)
John S. Petersen, Petersen Advanced Lithography (United States)


Published in SPIE Proceedings Vol. 7122:
Photomask Technology 2008
Hiroichi Kawahira; Larry S. Zurbrick, Editor(s)

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