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Proceedings Paper

Fast and simple modeling of non-rectangular transistors
Author(s): Jen-Yi Wuu; Fedor G. Pikus; Malgorzata Marek-Sadowska
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Paper Abstract

As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled nonrectangular gate device. The average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.

Paper Details

Date Published: 17 October 2008
PDF: 10 pages
Proc. SPIE 7122, Photomask Technology 2008, 71223S (17 October 2008); doi: 10.1117/12.801541
Show Author Affiliations
Jen-Yi Wuu, Univ. of California, Santa Barbara (United States)
Fedor G. Pikus, Mentor Graphics Corp. (United States)
Malgorzata Marek-Sadowska, Univ. of California, Santa Barbara (United States)


Published in SPIE Proceedings Vol. 7122:
Photomask Technology 2008
Hiroichi Kawahira; Larry S. Zurbrick, Editor(s)

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