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Proceedings Paper

Single exposure is still alive: gate patterning at 45nm technology node
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Paper Abstract

A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm technology node. They consist mainly of the introduction of a new software for optical proximity correction, the introduction of model based process window correction, the switch to model based etch proximity correction, and support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.

Paper Details

Date Published: 17 October 2008
PDF: 10 pages
Proc. SPIE 7122, Photomask Technology 2008, 71220W (17 October 2008); doi: 10.1117/12.801526
Show Author Affiliations
Klaus Herold, Infineon Technologies NA Corp. (United States)
Donald J. Samuels, IBM Systems and Technology Group (United States)
Derren Dunn, IBM Systems and Technology Group (United States)
Amr Abdo, IBM Systems and Technology Group (United States)
Chandrasekhar Sarma, Infineon Technologies NA Corp. (United States)


Published in SPIE Proceedings Vol. 7122:
Photomask Technology 2008
Hiroichi Kawahira; Larry S. Zurbrick, Editor(s)

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