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Proceedings Paper

A study of mask specification in spacer patterning technology
Author(s): Hidefumi Mukai; Yuuji Kobayashi; Shinji Yamaguchi; Kenji Kawano; Kohji Hashimoto
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Paper Abstract

A spacer patterning technology (SP) has the possibility of extending optical lithography to below 40nm half-pitch devices. Since the spacer patterning process necessitates somewhat more complicated wafer process flow, the CD variation on wafers involves more process error sources compared with conventional exposure patterning process. This implies that, for the spacer patterning process innovation in determining specifications for each unit process is requried. In particular, it is important to determine mask-related specifications in order to select high-end mask fabrication strategies for mask writing tools, mask process development, materials, inspection tools, and so on. The purpose of this paper is to discuss how to consider mask specification in spacer patterning process for 40nm half-pitch and beyond.

Paper Details

Date Published: 19 May 2008
PDF: 8 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 702812 (19 May 2008); doi: 10.1117/12.800464
Show Author Affiliations
Hidefumi Mukai, Toshiba Corp. (Japan)
Yuuji Kobayashi, Toshiba Corp. (Japan)
Shinji Yamaguchi, Toshiba Corp. (Japan)
Kenji Kawano, Toshiba Corp. (Japan)
Kohji Hashimoto, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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