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Proceedings Paper

Logic device scaling trend in ITRS 2007
Author(s): Kiyotaka Imai
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Paper Abstract

Logic CMOS device scaling trend is described along the International Technology Roadmap for Semiconductors (ITRS) 2007 edition. For transistor performance improvement, geometrical scaling of gate length still plays an important role. At the same time, equivalent scaling such as metal gate and mobility enhancement is also indispensable. In order to break through the improvement limitation of planar bulk structure, new transistor structure such as FinFET will be introduced from 2010 or 2011 time frame. In long term, alternative materials and structures will be required to realize extremely high ballistic transport.

Paper Details

Date Published: 19 May 2008
PDF: 8 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 702802 (19 May 2008); doi: 10.1117/12.796009
Show Author Affiliations
Kiyotaka Imai, NEC Electronics Corp. (Japan)


Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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