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Proceedings Paper

A new pipelined VLSI architecture for JPEG-LS compression algorithm
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Paper Abstract

An innovative VLSI architecture for JPEG-LS compression algorithm is proposed, which implements real-time image compression either in near lossless mode or in lossless mode. The proposed architecture mainly includes four parallel pipelines, in which four pixels from four continuous lines could be processed simultaneously with a specific coding scan sequence, which ensures low complexity and real-time data processing. Our VLSI architecture is implemented on a Xilinx XC2VP30 FPGA. The experiment results show that our hardware system has the same results in image quality and compression rate as the standard JPEG-LS method and the processing speed of our system is four times more than that of traditional method.

Paper Details

Date Published: 5 September 2008
PDF: 6 pages
Proc. SPIE 7084, Satellite Data Compression, Communication, and Processing IV, 70840O (5 September 2008); doi: 10.1117/12.794543
Show Author Affiliations
Jie Lei, Xidian Univ. (China)
Yunsong Li, Xidian Univ. (China)
Fanqiang Kong, Xidian Univ. (China)
Chengke Wu, Xidian Univ. (China)


Published in SPIE Proceedings Vol. 7084:
Satellite Data Compression, Communication, and Processing IV
Bormin Huang; Roger W. Heymann; Joan Serra-Sagristà, Editor(s)

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