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Proceedings Paper

Optimization of the final adder stage of fast multipliers
Author(s): Sean Laughlin; Sabrina Smith; Paul Zucknick; Earl E. Swartzlander
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Paper Abstract

Fast multipliers consist of an array of AND gates, a bit reduction stage, and a final two-operand addition. There are three widely recognized types of fast multipliers: Wallace, Dadda, and reduced area. These multipliers are distinguished by their techniques for the bit reduction stage; however, little research has been invested in the optimization of the final addition stage. This paper presents an approach for investigating the optimal final adder structure for the three types of fast multipliers. Multiple designs are characterized using the Virginia Tech 0.25 μm TSMC standard cell library and Synopsys Design Vision to determine area, power consumption, and critical delay compared with a traditional carry look ahead adder. A figure of merit that includes these measurements is used to compare the performance of the proposed adders. Although this analysis neglects loading, interconnect, and several other parameters that are needed to accurately model the multipliers in a modern VLSI process technology, the results obtained using the figure of merit suggest that the final adder in each of the three fast multipliers can indeed be optimized.

Paper Details

Date Published: 3 September 2008
PDF: 12 pages
Proc. SPIE 7074, Advanced Signal Processing Algorithms, Architectures, and Implementations XVIII, 70740L (3 September 2008); doi: 10.1117/12.794300
Show Author Affiliations
Sean Laughlin, Univ. of Texas at Austin (United States)
Sabrina Smith, Univ. of Texas at Austin (United States)
Paul Zucknick, Univ. of Texas at Austin (United States)
Earl E. Swartzlander, Univ. of Texas at Austin (United States)

Published in SPIE Proceedings Vol. 7074:
Advanced Signal Processing Algorithms, Architectures, and Implementations XVIII
Franklin T. Luk, Editor(s)

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