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Proceedings Paper

Electrical metrics for lithographic line-end tapering
Author(s): Puneet Gupta; Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park
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Paper Abstract

A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this regard. In this work, we calculate the Ion and Ioff impact of line-end taper shapes as well as line-end length. The proposed models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ΔIon and ΔIoff. Finally, the electrical metric for line-end printing is defined as expected change in Ion or Ioff under a given overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large variety of taper shapes to characterize electrical impact.

Paper Details

Date Published: 19 May 2008
PDF: 12 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70283A (19 May 2008); doi: 10.1117/12.793117
Show Author Affiliations
Puneet Gupta, Univ. of California, Los Angeles (United States)
Kwangok Jeong, Univ. of California, San Diego (United States)
Andrew B. Kahng, Univ. of California, San Diego (United States)
Chul-Hong Park, Univ. of California, San Diego (United States)

Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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