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Proceedings Paper

Image placement error of photomask due to pattern loading effect: analysis and correction technique for sub-45 nm node
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Paper Abstract

As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an important factor to be reduced. Especially, by the development of double exposure technique (DET) or double patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly. Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4 nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors, here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction method.

Paper Details

Date Published: 19 May 2008
PDF: 13 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70281X (19 May 2008); doi: 10.1117/12.793074
Show Author Affiliations
Jin Choi, Samsung Electronics Co., Ltd. (South Korea)
Sang Hee Lee, Samsung Electronics Co., Ltd. (South Korea)
Dongseok Nam, Samsung Electronics Co., Ltd. (South Korea)
Byung Gook Kim, Samsung Electronics Co., Ltd. (South Korea)
Sang-Gyun Woo, Samsung Electronics Co., Ltd. (South Korea)
Han Ku Cho, Samsung Electronics Co., Ltd. (South Korea)


Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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