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Proceedings Paper

Model-based mask verification on critical 45nm logic masks
Author(s): F. Sundermann; F. Foussadier; T. Takigawa; J. Wiley; A. Vacca; L. Depre; G. Chen; S. Bai; J.-S. Wang; R. Howell; V. Arnoux; K. Hayano; S. Narukawa; S. Kawashima; H. Mohri; N. Hayashi; H. Miyashita; Y. Trouiller; F. Robert; F. Vautrin; G. Kerrien; J. Planchot; C. Martinelli; J. L. Di-Maria; V. Farys; B. Vandewalle; L. Perraud; J. C. Le Denmat; A. Villaret; C. Gardin; E. Yesilada; M. Saied
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Paper Abstract

In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by creating a short-range mask process model (MPM) for each unique mask process and a long-range CD uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1) and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with the current results of this new dynamic application to improve hot spot verification through Brion Technologies' model-based mask verification loop.

Paper Details

Date Published: 19 May 2008
PDF: 12 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70280U (19 May 2008); doi: 10.1117/12.793037
Show Author Affiliations
F. Sundermann, STMicroelectronics (France)
F. Foussadier, STMicroelectronics (France)
T. Takigawa, Brion Technologies (United States)
J. Wiley, Brion Technologies (United States)
A. Vacca, Brion Technologies (United States)
L. Depre, Brion Technologies (United States)
G. Chen, Brion Technologies (United States)
S. Bai, Brion Technologies (United States)
J.-S. Wang, Brion Technologies (United States)
R. Howell, Brion Technologies (United States)
V. Arnoux, Brion Technologies (United States)
K. Hayano, Dai Nippon Printing Co. (Japan)
S. Narukawa, Dai Nippon Printing Co. (Japan)
S. Kawashima, Dai Nippon Printing Co. (Japan)
H. Mohri, Dai Nippon Printing Co. (Japan)
N. Hayashi, Dai Nippon Printing Co. (Japan)
H. Miyashita, Dai Nippon Printing Co. (Japan)
Y. Trouiller, CEA/LETI (France)
F. Robert, STMicroelectronics (France)
F. Vautrin, STMicroelectronics (France)
G. Kerrien, STMicroelectronics (France)
J. Planchot, STMicroelectronics (France)
C. Martinelli, STMicroelectronics (France)
J. L. Di-Maria, CEA/LETI (France)
V. Farys, STMicroelectronics (France)
B. Vandewalle, STMicroelectronics (France)
L. Perraud, CEA/LETI (France)
J. C. Le Denmat, STMicroelectronics (France)
A. Villaret, STMicroelectronics (France)
C. Gardin, STMicroelectronics (France)
E. Yesilada, STMicroelectronics (France)
M. Saied, STMicroelectronics (France)


Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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