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Proceedings Paper

Yield-centric layout optimization with precise quantification of lithographic yield loss
Author(s): Sachiko Kobayashi; Suigen Kyoh; Koichi Kinoshita; Yukihiro Urakawa; Eiji Morifuji; Satoshi Kuramoto; Soichi Inoue
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Paper Abstract

Continuous shrinkage of the design rule in LSI devices brings about greater difficulty in the manufacturing process. Since not only process engineers' efforts but also yield-centric layout optimization is becoming increasingly important, such optimization has recently become a focus of interest. One of the approached is lithographic hotspot modification in design data. Using lithography compliance check and a hotspot fixing system in the early stage of design, design with wider process margin can be obtained. In order to achieve higher process yield after hotspot fixing, layout should be carefully optimized to decrease pattern-dependent yield loss. Since yield value for the design will fluctuate sensitively as designed pattern are modified, pattern should be optimized based on a comprehensive consideration of yield loss covering parametric, systematic and random effects. In this work, using lithography simulation, a lithographic yield loss model is defined and applied for precise quantification of process yield loss in 45 nm logic design. Yield loss values of each cell for lithographic, parametric and random effects are estimated, and then layouts through multiple layers are optimized to decrease total yield loss. As a result, litho-yield loss is greatly improved without deteriorating total yield value. Thus, layout is obtained that reflects an awareness of overall process yield.

Paper Details

Date Published: 19 May 2008
PDF: 8 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70280O (19 May 2008); doi: 10.1117/12.793031
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Suigen Kyoh, Toshiba Corp. (Japan)
Koichi Kinoshita, Toshiba Corp. (Japan)
Yukihiro Urakawa, Toshiba Corp. (Japan)
Eiji Morifuji, Toshiba Corp. (Japan)
Satoshi Kuramoto, Takumi Technology KK (Japan)
Soichi Inoue, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

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