Share Email Print

Proceedings Paper

Predictive modeling of lithography-induced linewidth variation
Author(s): Andrew B. Kahng; Swamy V. Muddu
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this work, we develop a predictive model of device linewidths after optical proximity correction (OPC) across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. To model litho effects on 2D poly geometries in standard cell layouts, we rigorously identify layout parameters that affect the litho contour. We classify gate poly (devices) into different categories based on their geometric parameters as well as those of neighboring field poly shapes. To create a model, we create a design of experiments (DOE) for all device categories and perform OPC followed by through-process window litho simulation. To limit the runtime of OPC and litho simulation for the DOE, we reduce the layout parameter space with a rigorously qualified methodology for filtering out unimportant parameters. To allow prediction of the device contour, we model the device edge placement error (EPE) using a response surface methodology followed by polynomial regression. We have implemented our predictive linewidth modeling with foundry 90nm and 65nm technology, along with industry-strength OPC models and recipes. Using the regression models, we have performed prediction on standard-cell blocks and achieved a 3σ prediction accuracy of 2nm across the process window.

Paper Details

Date Published: 19 May 2008
PDF: 14 pages
Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70280M (19 May 2008); doi: 10.1117/12.793029
Show Author Affiliations
Andrew B. Kahng, Univ. of California, San Diego (United States)
Swamy V. Muddu, Univ. of California, San Diego (United States)

Published in SPIE Proceedings Vol. 7028:
Photomask and Next-Generation Lithography Mask Technology XV
Toshiyuki Horiuchi, Editor(s)

© SPIE. Terms of Use
Back to Top