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Proceedings Paper

DSP algorithms in FPGA: proposition of a new architecture
Author(s): Piotr Kolasinski; Wojciech Zabolotny
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Paper Abstract

This paper presents a new reconfigurable architecture created in FPGA which is optimized for DSP algorithms like digital filters or digital transforms. The architecture tries to combine advantages of typical architectures like DSP processors and datapath architecture, while avoiding their drawbacks. The architecture is built from blocks called Operational Units (OU). Each Operational Unit contains the Control Unit (CU), which controls its operation. The Operational Units may operate in parallel, which shortens the processing time. This structure is also highly flexible, because all OUs may operate independently, executing their own programs. User may customize connections between units and modify architecture by adding new modules.

Paper Details

Date Published: 28 December 2007
PDF: 5 pages
Proc. SPIE 6937, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2007, 69370M (28 December 2007); doi: 10.1117/12.784572
Show Author Affiliations
Piotr Kolasinski, Warsaw Univ. of Technology (Poland)
Wojciech Zabolotny, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 6937:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2007

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