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Proceedings Paper

Real-time dynamic PC image generation techniques for high performance and high dynamic range fidelity
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Paper Abstract

AMRDEC has developed and implemented new techniques for rendering real-time 32-bit floating point energy-conserved dynamic scenes using commercial-off-the-shelf (COTS) Personal Computer (PC) based hardware and high performance nVidia Graphics Processing Units (GPU). The AMRDEC IGStudio rendering framework with the real-time Joint Scientific Image Generator (JSIG) core has been integrated into numerous AMRDEC Hardware-in-the-loop (HWIL) facilities, successfully replacing the lower fidelity legacy SGI hardware and software. JSIG uses high dynamic range unnormalized radiometric 32-bit floating point rendering through the use of GPU frame buffer objects (FBOs). A high performance nested zoom anti-aliasing (NZAA) technique was developed to address performance and geometric errors of past zoom anti-aliasing (ZAA) implementations. The NZAA capability for multi-object and occluded object representations includes: cluster ZAA, object ZAA, sub-object ZAA, and point source generation for unresolved objects. This technique has an optimal 128x128 pixel asymmetrical field-of-view zoom. The current NZAA capability supports up to 8 objects in real-time with a near future capability of increasing to a theoretical 128 objects in real-time. JSIG performs other dynamic entity effects which are applied in vertex and fragment shaders. These effects include floating point dynamic signature application, dynamic model ablation heating models, and per-material thermal emissivity rolloff interpolated on a per-pixel zoomed window basis. JSIG additionally performs full scene per-pixel effects in a post render process. These effects include real-time convolutions, optical scene corrections, per-frame calibrations, and energy distribution blur used to compensate for projector element energy limitations.

Paper Details

Date Published: 11 April 2008
PDF: 18 pages
Proc. SPIE 6942, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIII, 69420K (11 April 2008); doi: 10.1117/12.782445
Show Author Affiliations
Dennis H. Bunfield, Davidson Technologies, Inc. (United States)
Darian E. Trimble, Davidson Technologies, Inc. (United States)
Thomas Fronckowiak, Jr., Davidson Technologies, Inc. (United States)
Gary Ballard, U.S. Army Aviation and Missile Research, Development and Engineering Ctr. (United States)
Joesph Morris, U.S. Army Aviation and Missile Research, Development and Engineering Ctr. (United States)


Published in SPIE Proceedings Vol. 6942:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIII
Robert Lee Murrer, Editor(s)

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