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Proceedings Paper

Design and implementation of high dynamic GNSS digital receiver
Author(s): Hanmei Li; Shengqun Geng; Ce Wang; Yong Xu; Qishan Zhang
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Paper Abstract

The paper presents a scheme of high dynamic GNSS digital receiver using FPGA xc4vsx55 of XILINX and DSP TMS320VC6701 of TI as core controller. Besides brief introduction of scheme design and hardware structure, the paper comprehensively introduces design and implementation of algorithms of fast acquisition and tracking of spread spectrum signal in high dynamic environment. Through optimized design, fast acquisition and tracking of both C code (coarse ranging code) and P code (precision ranging code) are realized in one chip of FPGA, under the control of DSP. Employing FFT-based fast acquisition algorithm, acquisition unit realizes the fast acquisition by duplicated using two FFT/IFFT units with time-sharing fashion, and other optimized FFT calculation structures. Carrier tracking loop is realized by adopting FLL+PLL method which using FLL tracking carrier Doppler shift with greater bandwidth making loop closed rapidly and using PLL precisely tracking carrier phase so as to achieve perfect tracking effects. PN code tracking loop is realized by using multiple non-coherent DLLs with various correlation spacing, which satisfying the requirements of larger tracking range as well as higher tracking precision by using broad spacing accomplishing initial tracking and narrow spacing realizing high precision tracking.

Paper Details

Date Published: 10 November 2007
PDF: 7 pages
Proc. SPIE 6795, Second International Conference on Space Information Technology, 67957V (10 November 2007); doi: 10.1117/12.780343
Show Author Affiliations
Hanmei Li, Beihang Univ. (China)
Shengqun Geng, Beihang Univ. (China)
Ce Wang, Beihang Univ. (China)
Yong Xu, Beihang Univ. (China)
Qishan Zhang, Beihang Univ. (China)

Published in SPIE Proceedings Vol. 6795:
Second International Conference on Space Information Technology
Cheng Wang; Shan Zhong; Jiaolong Wei, Editor(s)

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