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Proceedings Paper

Context analysis and validation of lithography induced systematic variations in 65nm designs
Author(s): Arjun Rajagopal; Anand Rajaram; Raguram Damodaran; Frank Cano; Srinivas Swaminathan; Clive Bittlestone; Mark Terry; Mark Mason; Yajun Ran; Haizhou Chen; Robert Ritchie; Bala Kasthuri; Jac Condella; Philippe Hurat; Nishath Verghese
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Paper Abstract

The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a real design.

Paper Details

Date Published: 19 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250A (19 March 2008); doi: 10.1117/12.778836
Show Author Affiliations
Arjun Rajagopal, Texas Instruments, Inc. (United States)
Anand Rajaram, Texas Instruments, Inc. (United States)
Raguram Damodaran, Texas Instruments, Inc. (United States)
Frank Cano, Texas Instruments, Inc. (United States)
Srinivas Swaminathan, Texas Instruments, Inc. (United States)
Clive Bittlestone, Texas Instruments, Inc. (United States)
Mark Terry, Texas Instruments, Inc. (United States)
Mark Mason, Texas Instruments, Inc. (United States)
Yajun Ran, Cadence Design Systems, Inc. (United States)
Haizhou Chen, Cadence Design Systems, Inc. (United States)
Robert Ritchie, Cadence Design Systems, Inc. (United States)
Bala Kasthuri, Cadence Design Systems, Inc. (United States)
Jac Condella, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Nishath Verghese, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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