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Proceedings Paper

An efficient real time superresolution ASIC system
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Paper Abstract

Superresolution of images is an important step in many applications like target recognition where the input images are often grainy and of low quality due to bandwidth constraints. In this paper, we present a real-time superresolution application implemented in ASIC/FPGA hardware, and capable of 30 fps of superresolution by 16X in total pixels. Consecutive frames from the video sequence are grouped and the registered values between them are used to fill the pixels in the higher resolution image. The registration between consecutive frames is evaluated using the algorithm proposed by Schaum et al. The pixels are filled by averaging a fixed number of frames associated with the smallest error distances. The number of frames (the number of nearest neighbors) is a user defined parameter whereas the weights in the averaging process are decided by inverting the corresponding smallest error distances. Wiener filter is used to post process the image. Different input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as the hardware, which gives us a fine balance between the number of bits and performance. The algorithm performs with real time speed with very impressive superresolution results.

Paper Details

Date Published: 15 April 2008
PDF: 8 pages
Proc. SPIE 6957, Enhanced and Synthetic Vision 2008, 695709 (15 April 2008); doi: 10.1117/12.778108
Show Author Affiliations
Dikpal Reddy, FastVDO Inc. (United States)
Zhanfeng Yue, FastVDO Inc. (United States)
Pankaj Topiwala, FastVDO Inc. (United States)


Published in SPIE Proceedings Vol. 6957:
Enhanced and Synthetic Vision 2008
Jeff J. Güell; Maarten Uijt de Haag, Editor(s)

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