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Proceedings Paper

VARAN: variability analysis for memory cell robustness
Author(s): Gideon Reisfeld; Dmitry Messerman; Nir Bone; Adi Lazar
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Paper Abstract

Increasing memory array sizes and low operating voltages in modern ICs expose the IC to extremely low failure rates of single memory cells. The failure probability is affected by variations in the process of IC fabrication, which yield varying transistor parameters. This may cause an erratic certification of designs that may have a low production yield. VARAN relies on analytical methods that yield controlled precision calculations involving a minimum of circuit simulation. Furthermore, VARAN is equipped with a built-in sensitivity analysis mechanism that can guide the designer as to which parameters are significant for robust design. The flow starts by setting a circuit simulation infrastructure. Each simulation returns a value of fail or pass for a given set of circuit parameters (i.e. transistor size) and environmental parameters. The probability of failure is calculated by integration over the design parameter space. VARAN uses a novel response surface modeling (RSM) to reduce the number of simulations that are needed for low probability calculations. The RSM relies on an adaptive fitting, which is capable of modeling intricate behaviors which require many parameters using ordinary polynomial modeling, with a minimal number of terms. VARAN was tested over synthetic and real circuit data yielding extremely low failure probabilities.

Paper Details

Date Published: 4 March 2008
PDF: 9 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250L (4 March 2008); doi: 10.1117/12.777269
Show Author Affiliations
Gideon Reisfeld, Intel Israel (Israel)
Dmitry Messerman, Intel Israel (Israel)
Nir Bone, Intel Israel (Israel)
Adi Lazar, F28 ENG (Israel)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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