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Proceedings Paper

FPGA design of MOMS-based sampling rate converters
Author(s): Uwe Meyer-Bäse
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Paper Abstract

In this paper we describe design options when implementing sampling rate converters with FPGAs. We first review typical designs using IIR and FFT-based systems and then show implementations of fractional sampling rate changer ranging from Lagrange, B-spline to recently introduced C-MOMS and O-MOMS designs. Speed, area and error performance results for the circuits designed in VHDL are provided.

Paper Details

Date Published: 3 April 2008
PDF: 12 pages
Proc. SPIE 6979, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks VI, 697906 (3 April 2008); doi: 10.1117/12.777231
Show Author Affiliations
Uwe Meyer-Bäse, Florida State Univ. (United States)


Published in SPIE Proceedings Vol. 6979:
Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks VI
Harold H. Szu; F. Jack Agee, Editor(s)

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