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Proceedings Paper

Enabling technology scaling with "in production" lithography processes
Author(s): Tejas Jhaveri; Andrzej Strojwas; Larry Pileggi; Vyachelav Rovner
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Paper Abstract

As the industry hits a road block with RETs that attempt to aggressively scale k1, we propose to extend the life of optical lithography by a complete co-optimization between circuit choices, layout patterns and lithography. We demonstrate that the judicious selection of a small number of layout patterns along with the appropriate circuit topologies would not only enable k1 relaxation but also efficient implementation of circuits. Additionally, in this paper, we discuss the use of regular design fabrics to extend the life of current generation lithography equipment. We will introduce the Front End of Line (FEOL) limited regular design fabric. The metal 1 patterns for this fabric are selected such that we can utilize a 1.2 NA 32nm metal 1 lithography process without any area penalty with respect to standard cells with conventional design rules, which require a 32nm metal 1 process with a rather unrealistic k1 of 0.35 while using a more advanced 1.35 NA tool. We also demonstrate simulation results on 2-dimensional layout patterns. The results suggest that smart selection of layout patterns can enable the extension of single exposure lithography to a 32nm production lithography process.

Paper Details

Date Published: 7 March 2008
PDF: 10 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69240K (7 March 2008); doi: 10.1117/12.776484
Show Author Affiliations
Tejas Jhaveri, Carnegie Mellon Univ. (United States)
PDF Solutions, Inc. (United States)
Andrzej Strojwas, Carnegie Mellon Univ. (United States)
PDF Solutions, Inc. (United States)
Larry Pileggi, Carnegie Mellon Univ. (United States)
PDF Solutions, Inc. (United States)
Vyachelav Rovner, Carnegie Mellon Univ. (United States)
PDF Solutions, Inc. (United States)


Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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