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Proceedings Paper

Advanced profile control and the impact of sidewall angle at gate etch for critical nodes
Author(s): Hyung Lee; Alok Ranjan; Dan Prager; Kenneth A Bandy; Eric Meyette; Radha Sundararajan; Anita Viswanathan; Asao Yamashita; Merritt Funk
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Paper Abstract

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.

Paper Details

Date Published: 22 March 2008
PDF: 13 pages
Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69220T (22 March 2008); doi: 10.1117/12.774962
Show Author Affiliations
Hyung Lee, Tokyo Electron America, Inc. (United States)
Alok Ranjan, Tokyo Electron America, Inc. (United States)
Dan Prager, Tokyo Electron America, Inc. (United States)
Kenneth A Bandy, IBM Microelectronics (United States)
Eric Meyette, IBM Microelectronics (United States)
Radha Sundararajan, Tokyo Electron America, Inc. (United States)
Anita Viswanathan, Tokyo Electron America, Inc. (United States)
Asao Yamashita, Tokyo Electron America, Inc. (United States)
Merritt Funk, Tokyo Electron America, Inc. (United States)


Published in SPIE Proceedings Vol. 6922:
Metrology, Inspection, and Process Control for Microlithography XXII
John A. Allgair; Christopher J. Raymond, Editor(s)

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