Share Email Print
cover

Proceedings Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Paper Details

Date Published: 17 March 2008
PDF: 10 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250E (17 March 2008); doi: 10.1117/12.774581
Show Author Affiliations
Steve Prins, Texas Instruments, Inc. (United States)
James Blatchford, Texas Instruments, Inc. (United States)
Simon Chang, Texas Instruments, Inc. (United States)
Lewis Flanagin, Texas Instruments, Inc. (United States)
Scott Jessen, Texas Instruments, Inc. (United States)
Sean O'Brien, Texas Instruments, Inc. (United States)
Guangming Xiao, Luminescent Technologies, Inc. (United States)
Timothy Lin, Luminescent Technologies, Inc. (United States)
Thuc Dam, Luminescent Technologies, Inc. (United States)
Bob Gleason, Luminescent Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top