Share Email Print
cover

Proceedings Paper

Design and realization of the baseband processor in satellite navigation and positioning receiver
Author(s): Dawei Zhang; Xiulin Hu; Chen Li
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The content of this paper is focused on the Design and realization of the baseband processor in satellite navigation and positioning receiver. Baseband processor is the most important part of the satellite positioning receiver. The design covers baseband processor's main functions include multi-channel digital signal DDC, acquisition, code tracking, carrier tracking, demodulation, etc. The realization is based on an Altera's FPGA device, that makes the system can be improved and upgraded without modifying the hardware. It embodies the theory of software defined radio (SDR), and puts the theory of the spread spectrum into practice. This paper puts emphasis on the realization of baseband processor in FPGA. In the order of choosing chips, design entry, debugging and synthesis, the flow is presented detailedly. Additionally the paper detailed realization of Digital PLL in order to explain a method of reducing the consumption of FPGA. Finally, the paper presents the result of Synthesis. This design has been used in BD-1, BD-2 and GPS.

Paper Details

Date Published: 10 November 2007
PDF: 6 pages
Proc. SPIE 6795, Second International Conference on Space Information Technology, 67954C (10 November 2007); doi: 10.1117/12.774573
Show Author Affiliations
Dawei Zhang, Huazhong Univ. of Science and Technology (China)
Xiulin Hu, Huazhong Univ. of Science and Technology (China)
Chen Li, Huazhong Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 6795:
Second International Conference on Space Information Technology

© SPIE. Terms of Use
Back to Top