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Proceedings Paper

Design of bus-on-chip core for micro-satellite avionics
Author(s): Youjun Liu; Zheng You; Bin Li; Xiangqi Zhang; Ziyang Meng
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Paper Abstract

This paper discusses a layout of bus-on-chip core referring to SoC thinking which is composed of six sections based on a physical chip of FPGA: multi-Processor cache coherence unit, external bus control module, TT&C module, Ethernet Mac interface, EDAC/DMA module, and AMBA bridges. Multi-processor cache coherence unit, as a key part of the bus core, is used to serve the rapid parallel computing by means of the breakthrough of write/read speed of EMS memory and enhances the reliability of OBC with the service of supporting the hot standby of redundancy and the reconfiguration of fault-tolerance. External bus control module is made to support the PnP of external components applying varieties of buses, which is designed by means of soft-core in order to adapt the variation of macro-design and improve the flexibility of external application. TT&C module is the interface of subsystems of telemetry, telecommand and communication, which involves the protocols of HDLC. Ethernet Mac interface based on TCP/IP acts as the access of ISL for formation flying, constellation, etc. EDAC/DMA module mainly manages the data exchange between AMBA bus and RAM, and assigns DMA for the payloads.

Paper Details

Date Published: 10 November 2007
PDF: 5 pages
Proc. SPIE 6795, Second International Conference on Space Information Technology, 67950Q (10 November 2007); doi: 10.1117/12.773758
Show Author Affiliations
Youjun Liu, Tsinghua Univ. (China)
Hefei Electronic Engineering Institute (China)
Zheng You, Tsinghua Univ. (China)
Bin Li, Tsinghua Univ. (China)
Xiangqi Zhang, Tsinghua Univ. (China)
Ziyang Meng, Tsinghua Univ. (China)


Published in SPIE Proceedings Vol. 6795:
Second International Conference on Space Information Technology
Cheng Wang; Shan Zhong; Jiaolong Wei, Editor(s)

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