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Proceedings Paper

Hypersensitive parameter-identifying ring oscillators for lithography process monitoring
Author(s): Lynn Tao-Ning Wang; Wojtek J. Poppe; Liang-Teck Pang; Andrew R. Neureuther; Elad Alon; Borivoje Nikolic
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Paper Abstract

This paper applies process and circuit simulation to examine plausible explanations for measured differences in ring oscillator frequencies and to develop layout and electronic circuit concepts that have increased sensitivity to lithographic parameters. Existing 90nm ring oscillator test chip measurements are leveraged, and the performance of ring oscillator circuit is simulated across the process parameter variation space using HSPICE and the Parametric Yield Simulator in the Collaborative Platform for DfM. These simulation results are then correlated with measured ring oscillator frequencies to directly extract the variation in the underlying parameter. Hypersensitive gate layouts are created by combining the physical principles in which the effects of illumination, focus, and pattern geometry interact. Using these principles and parametric yield simulations, structures that magnify the focus effects have been found. For example, by using 90° phase shift probe, parameter-specific layout monitors are shown to be five times more sensitive to focus than that of an isolated line. On the design side, NMOS or PMOS-specific electrical circuits are designed, implemented, and simulated in HSPICE.

Paper Details

Date Published: 18 March 2008
PDF: 10 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250P (18 March 2008); doi: 10.1117/12.773184
Show Author Affiliations
Lynn Tao-Ning Wang, Univ. of California, Berkeley (United States)
Wojtek J. Poppe, Univ. of California, Berkeley (United States)
Liang-Teck Pang, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)
Elad Alon, Univ. of California, Berkeley (United States)
Borivoje Nikolic, Univ. of California, Berkeley (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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