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Development of layout split algorithms and printability evaluation for double patterning technology
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Paper Abstract

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brion's TachyoTM system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

Paper Details

Date Published: 7 March 2008
PDF: 10 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69243M (7 March 2008); doi: 10.1117/12.773107
Show Author Affiliations
Tsann-Bim Chiou, ASML TDC Asia (Taiwan)
Robert Socha, ASML TDC USA (United States)
Hong Chen, ASML Brion (United States)
Luoqi Chen, ASML Brion (United States)
Stephen Hsu, ASML Brion (United States)
Peter Nikolsky, ASML (Netherlands)
Anton van Oosten, ASML (Netherlands)
Alek C. Chen, ASML TDC Asia (Taiwan)

Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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