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Proceedings Paper

Impact of gate line edge roughness on double-gate FinFET performance variability
Author(s): Kedar Patel; Tsu-Jae King Liu; Costas Spanos
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Paper Abstract

The impact of gate line edge roughness (LER) on the performance variability of 32nm double-gate (DG) FinFETs is investigated using a framework that links device performance to commonly used LER descriptors, namely correlation length (ξ), RMS amplitude or standard deviation (σ) of the line edge from its mean value, and roughness exponent (α). This modeling approach is more efficient than Monte-Carlo TCAD simulations, and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Additionally, a spacer-defined gate electrode provides for dramatically reduced variability in device performance compared to a resist-defined gate electrode, which indicates that gate-length mismatch contributes more to variability in performance than lateral offset between the front and the back gate.

Paper Details

Date Published: 19 March 2008
PDF: 10 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251I (19 March 2008); doi: 10.1117/12.773065
Show Author Affiliations
Kedar Patel, SanDisk Inc. (United States)
Univ. of California, Berkeley (United States)
Tsu-Jae King Liu, Univ. of California, Berkeley (United States)
Costas Spanos, Univ. of California, Berkeley (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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