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Proceedings Paper

Resolution enhancement techniques in 65 nm node nested-hole patterning
Author(s): Hyesung Lee; Jaeyoung Choi; Jeahee Kim; Jaewon Han; Keun-Young Kim
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Paper Abstract

In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process, regarding porcess cost redcution and easy access to RETs.

Paper Details

Date Published: 1 April 2008
PDF: 8 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69244B (1 April 2008); doi: 10.1117/12.773017
Show Author Affiliations
Hyesung Lee, DongbuHiTek (South Korea)
Jaeyoung Choi, DongbuHiTek (South Korea)
Jeahee Kim, DongbuHiTek (South Korea)
Jaewon Han, DongbuHiTek (South Korea)
Keun-Young Kim, International Technology Alliances, Inc. (United States)

Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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