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A comprehensive model of process variability for statistical timing optimization
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Paper Abstract

As technologies scale, the impact of process variations to circuit performance and power consumption is increasingly significant. In order to improve the efficiency of statistical circuit optimization, a better understanding of the relationship between circuit variability and process variation is needed. Our work proposes a hierarchical variability model, which addresses both systematic and random variations at wafer, field, die, and device level, and spatial correlation artifacts are captured implicitly. Finally, layout dependent effects are incorporated as an additive component. The model is verified by applying to 90nm ring oscillator measurement data and can be used for variability prediction and optimization.

Paper Details

Date Published: 4 March 2008
PDF: 11 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251G (4 March 2008); doi: 10.1117/12.772980
Show Author Affiliations
Kun Qian, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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