Share Email Print

Proceedings Paper

Fabrication of defect-free full-field pixelated phase mask
Author(s): Wen-Hao Cheng; Jeff Farnsworth; Wai Kwok; Andrew Jamieson; Nathan Wilcox; Matt Vernon; Karmen Yung; Yi-Ping Liu; Jun Kim; Eric Frendberg; Scott Chegwidden; Richard Schenker; Yan Borodovsky
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair, disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor device yield. To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and integrated upstream in the optical model and design layout. The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced. Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse, were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield were verified downstream through silicon wafer print test to validate defect free mask performance.

Paper Details

Date Published: 7 March 2008
PDF: 10 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69241G (7 March 2008); doi: 10.1117/12.772955
Show Author Affiliations
Wen-Hao Cheng, Intel Corp. (United States)
Jeff Farnsworth, Intel Corp. (United States)
Wai Kwok, Intel Corp. (United States)
Andrew Jamieson, Intel Corp. (United States)
Nathan Wilcox, Intel Corp. (United States)
Matt Vernon, Intel Corp. (United States)
Karmen Yung, Intel Corp. (United States)
Yi-Ping Liu, Intel Corp. (United States)
Jun Kim, Intel Corp. (United States)
Eric Frendberg, Intel Corp. (United States)
Scott Chegwidden, Intel Corp. (United States)
Richard Schenker, Intel Corp. (United States)
Yan Borodovsky, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

© SPIE. Terms of Use
Back to Top