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Proceedings Paper

The use of EUV lithography to produce demonstration devices
Author(s): Bruno LaFontaine; Yunfei Deng; Ryoung-Han Kim; Harry J. Levinson; Sarah McGowan; Uzodinma Okoroanyanwu; Rolf Seltmann; Cyrus Tabery; Anna Tchikoulaeva; Tom Wallow; Obert Wood; John Arnold; Don Canaperi; Matthew Colburn; Kurt Kimmel; Chiew-Seng Koay; Erin Mclellan; Dave Medeiros; Satyavolu Papa Rao; Karen Petrillo; Yunpeng Yin; Hiroyuki Mizuno; Sander Bouten; Michael Crouse; Andre van Dijk; Youri van Dommelen; Judy Galloway; Sang-In Han; Bart Kessels; Brian Lee; Sjoerd Lok; Brian Niekrewicz; Bill Pierson; Robert Routh; Emil Schmit-Weaver; Kevin Cummings; James Word
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Paper Abstract

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1). This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results. Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

Paper Details

Date Published: 26 March 2008
PDF: 10 pages
Proc. SPIE 6921, Emerging Lithographic Technologies XII, 69210P (26 March 2008); doi: 10.1117/12.772933
Show Author Affiliations
Bruno LaFontaine, Advanced Micro Devices, Inc. (United States)
Yunfei Deng, Advanced Micro Devices, Inc. (United States)
Ryoung-Han Kim, Advanced Micro Devices, Inc. (United States)
Harry J. Levinson, Advanced Micro Devices, Inc. (United States)
Sarah McGowan, Advanced Micro Devices, Inc. (United States)
Uzodinma Okoroanyanwu, Advanced Micro Devices, Inc. (United States)
Rolf Seltmann, Advanced Micro Devices, Inc. (United States)
Cyrus Tabery, Advanced Micro Devices, Inc. (United States)
Anna Tchikoulaeva, AMD Saxony LLC & Co. KG (Germany)
Tom Wallow, Advanced Micro Devices, Inc. (United States)
Obert Wood, Advanced Micro Devices, Inc. (United States)
John Arnold, IBM Corp. (United States)
Don Canaperi, IBM Corp. (United States)
Matthew Colburn, IBM Corp. (United States)
Kurt Kimmel, IBM Corp. (United States)
Chiew-Seng Koay, IBM Corp. (United States)
Erin Mclellan, IBM Corp. (United States)
Dave Medeiros, IBM Corp. (United States)
Satyavolu Papa Rao, IBM Corp. (United States)
Karen Petrillo, IBM Corp. (United States)
Yunpeng Yin, IBM Corp. (United States)
Hiroyuki Mizuno, Toshiba America Electronics Components (United States)
Sander Bouten, ASML (United States)
Michael Crouse, ASML (United States)
Andre van Dijk, ASML (United States)
Youri van Dommelen, Toshiba America Electronics Components (United States)
Judy Galloway, Toshiba America Electronics Components (United States)
Sang-In Han, Toshiba America Electronics Components (United States)
Bart Kessels, Toshiba America Electronics Components (United States)
Brian Lee, Toshiba America Electronics Components (United States)
Sjoerd Lok, Toshiba America Electronics Components (United States)
Brian Niekrewicz, ASML (United States)
Bill Pierson, ASML (United States)
Robert Routh, ASML (United States)
Emil Schmit-Weaver, ASML (United States)
Kevin Cummings, ASML (United States)
James Word, Mentor Graphics (United States)


Published in SPIE Proceedings Vol. 6921:
Emerging Lithographic Technologies XII
Frank M. Schellenberg, Editor(s)

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