Share Email Print
cover

Proceedings Paper

APF pitch-halving for 22nm logic cells using gridded design rules
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF(R)-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela CanvaTM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

Paper Details

Date Published: 4 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251E (4 March 2008); doi: 10.1117/12.772905
Show Author Affiliations
Michael C. Smayling, Tela Innovations, Inc. (United States)
Christopher Bencher, Applied Materials, Inc. (United States)
Hao D. Chen, Applied Materials, Inc. (United States)
Huixiong Dai, Applied Materials, Inc. (United States)
Michael P. Duane, Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top