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Proceedings Paper

Shaping gate channels for improved devices
Author(s): Puneet Gupta; Andrew B. Kahng; Youngmin Kim; Saumil Shah; Dennis Sylvester
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Paper Abstract

With the increased need for low power applications, designers are being forced to employ circuit optimization methods that make tradeoffs between performance and power. In this paper, we propose a novel transistor-level optimization method. Instead of drawing the transistor channel as a perfect rectangle, this method involves reshaping the channel to create an optimized device that is superior in both delay and leakage to the original device. The method exploits the unequal drive and leakage current distributions across the transistor channel to find an optimal non-rectangular shape for the channel. In this work we apply this technique to circuit-level leakage reduction. By replacing every transistor in a circuit with its optimally shaped counterpart, we achieve 5% savings in leakage on average for a set of benchmark circuits, with no delay penalty. This improvement is achieved without any additional circuit optimization iterations, and is well suited to fit into existing design flows.

Paper Details

Date Published: 1 April 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250I (1 April 2008); doi: 10.1117/12.772889
Show Author Affiliations
Puneet Gupta, Univ. of California, Los Angeles (United States)
Andrew B. Kahng, Univ. of California, San Diego (United States)
Youngmin Kim, Univ. of Michigan (United States)
Saumil Shah, Blaze DFM, Inc. (United States)
Dennis Sylvester, Univ. of Michigan (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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