Share Email Print
cover

Proceedings Paper

32nm design rule evaluation through virtual patterning
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Lithography simulation has proven to be a technical enabler to shorten development cycle time and provide direction before next-generation exposure tools and processes are available. At the early stages of design rule definition for a new technology node, small critical areas of layout are of concern, and optical proximity correction (OPC) is required to allow full exploration of the 2D rule space. In this paper, we demonstrate the utility of fast, resist-model-based, OPC correction to explore process options and optimize 2D layout rules for advanced technologies. Unlike conventional OPC models that rely on extensive empirical CD-SEM measurements of real wafers, the resist-based OPC model for the correction is generated using measured bulk parameters of the photoresist such as dissolution rate. The model therefore provides extremely accurate analysis capability well in advance of access to advanced exposure tools. We apply this 'virtual patterning' approach to refine lithography tool settings and OPC strategies for a collection of 32-nm-node layout clips. Different OPC decorations including line biasing, serifs, and assist features, are investigated as a function of NA and illumination conditions using script-based optimization sequences. Best process conditions are identified based on optimal process window for a given set of random layouts. Simulation results, including resist profile and CD process window, are validated by comparison to wafer images generated on an older-generation exposure tool. The ability to quickly optimize OPC as a function of illumination setting in a single simulation package allows determination of optimum illumination source for random layouts faster and more accurately than what has been achievable in the past. This approach greatly accelerates design rule determination.

Paper Details

Date Published: 17 March 2008
PDF: 19 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692518 (17 March 2008); doi: 10.1117/12.772685
Show Author Affiliations
Scott Jessen, Texas Instruments, Inc. (United States)
James Blatchford, Texas Instruments, Inc. (United States)
Steve Prins, Texas Instruments, Inc. (United States)
Simon Chang, Texas Instruments, Inc. (United States)
Yiming Gu, Texas Instruments, Inc. (United States)
Mark Smith, KLA-Tencor Corp. (United States)
Dale Legband, KLA-Tencor Corp. (United States)
Chris Sallee, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top