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Proceedings Paper

Accurate device simulations through CD-SEM-based edge-contour extraction
Author(s): Eitan Shauly; Ovadya Menadeva; Rami Drori; Moran Cohen-Yasour; Israel Rotstein; Ram Peltinov; Avishai Bartov; Sergei Latinski; Amit Siany; Mark Geshesl
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Paper Abstract

A new methodology to predict changes in device performances due to systematic lithography and etch effects is described in this paper. Our methodology consists on Automatic Edge-Contour-Extraction (ECE) on Poly Over Active Layer, taking along the manufacturing variability. In general, the AMAT SEM (Scanning Electron Microscopy) ECE algorithm is based on CAD (GDS) to SEM pattern recognition, followed by CD based 2D edge extraction. Device modeling (using SPICE simulation) is used, to predict the nominal values as well as the device performances variability of the transistors drive current (Ion) and leakage current (Ioff). We used our method to compare a classical (simple rectangular) transistors and "U-Shape AA" transistors, both manufactured using Tower TS013LL (0.13um Low-Leakage) Platform. It was found, as predicted, that U-shape transistors have larger W distribution. However, "U-shape" also showed much tighter L distribution and the overall Ion spread is lower comparing to classical transistors. Also, U-Shape transistors found to have lower Lstdev (gate length distribution of each individual transistor). We also used the ECE methodology, to compare transistors of single side dog-bone to double-side dog-bone. Based on our work, we can predict that single-side dog-bone transistors, will have higher and larger Ioff distributions, and the overall Ioff speared along the wafer, will go up to a factor of x2.5.

Paper Details

Date Published: 4 April 2008
PDF: 9 pages
Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69221L (4 April 2008); doi: 10.1117/12.772648
Show Author Affiliations
Eitan Shauly, Tower Semiconductors (Israel)
Ovadya Menadeva, Applied Materials, Inc. (Israel)
Rami Drori, Tower Semiconductors (Israel)
Moran Cohen-Yasour, Tower Semiconductors (Israel)
Israel Rotstein, Tower Semiconductors (Israel)
Ram Peltinov, Applied Materials, Inc. (Israel)
Avishai Bartov, Applied Materials, Inc. (Israel)
Sergei Latinski, Applied Materials, Inc. (Israel)
Amit Siany, Applied Materials, Inc. (Israel)
Mark Geshesl, Applied Materials, Inc. (Israel)

Published in SPIE Proceedings Vol. 6922:
Metrology, Inspection, and Process Control for Microlithography XXII
John A. Allgair; Christopher J. Raymond, Editor(s)

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