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Proceedings Paper

Global and local factors of on-chip variation of gate length
Author(s): Morimi Osawa; Koji Hosono; Satoru Asai
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Paper Abstract

For accurate analysis of circuit performance, an understanding on-chip gate length variation is required. Non-systematic OCLV was measured by SEM and the results were analyzed after being divided into local and global factors. Simple empirical models of global and local variations were proposed, and fitting was done. In the fitting, measured mask variation was used, and on-chip variation of focus, dose, and LWR were fitting parameters. The fit of our model was very consistent with experimental result. Prediction of global and local variation using lithographic characters of patterns, such as EL, DOF, and MEEF, was enabled.

Paper Details

Date Published: 4 March 2008
PDF: 11 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692508 (4 March 2008); doi: 10.1117/12.772568
Show Author Affiliations
Morimi Osawa, Fujitsu, Ltd. (Japan)
Koji Hosono, Fujitsu, Ltd. (Japan)
Satoru Asai, Fujitsu, Ltd. (Japan)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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