Share Email Print
cover

Proceedings Paper

EBDW technology for EB shuttle at 65nm node and beyond
Author(s): T. Maruyama; M. Takakuwa; Y. Kojima; Y. Takahashi; K. Yamada; J. Kon; M. Miyajima; A. Shimizu; Y. Machida; H. Hoshino; H. Takita; S. Sugatani; H. Tsuchikawa
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

When manufacturing prototype devices or low volume custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We attempt to apply EBDW mainly to critical interconnect layers to reduce the mask expenditure for the reason of technical output reusability. For 65nm node production, new 300mm EB direct writer had been installed. The process technologies have also been developing to meet sufficient qualities and productivities.

Paper Details

Date Published: 20 March 2008
PDF: 10 pages
Proc. SPIE 6921, Emerging Lithographic Technologies XII, 69210H (20 March 2008); doi: 10.1117/12.772469
Show Author Affiliations
T. Maruyama, e-Shuttle Inc. (Japan)
M. Takakuwa, e-Shuttle Inc. (Japan)
Y. Kojima, e-Shuttle Inc. (Japan)
Y. Takahashi, e-Shuttle Inc. (Japan)
K. Yamada, e-Shuttle Inc. (Japan)
J. Kon, Fujitsu Labs. Ltd. (Japan)
M. Miyajima, Fujitsu Ltd. (Japan)
A. Shimizu, Fujitsu Ltd. (Japan)
Y. Machida, Fujitsu Ltd. (Japan)
H. Hoshino, Fujitsu Ltd. (Japan)
H. Takita, Fujitsu Ltd. (Japan)
S. Sugatani, e-Shuttle Inc. (Japan)
H. Tsuchikawa, e-Shuttle Inc. (Japan)


Published in SPIE Proceedings Vol. 6921:
Emerging Lithographic Technologies XII
Frank M. Schellenberg, Editor(s)

© SPIE. Terms of Use
Back to Top