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Proceedings Paper

Improvement on OPC completeness through pre-OPC hot spot detection and fix
Author(s): Yeonah Shim; Jaeyoung Choi; Jeahee Kim; Bo Su; Ping Zhang; Keun-Young Kim
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Paper Abstract

Design For Manufacturing (DFM) has been paid attention as the feature size on chip goes down below the k1 factor of 0.25. Lots of DFM related ideas have been come up, tried, and some of them adopted for wider process window and as a result, higher yield. As the minimum features are getting shrunk, the design rules become more complicated, but still not good enough to describe the complexity and limitation of certain patterns that imposes narrow process window, or even failure of device. Thus, it becomes essential to identify, correct, or remove the litho-unfriendly patterns (more widely called as hot spots), before OPC. One of the efforts is to write a DFM rules in addition to conventional DRC rules. In this study, we use the software, called YAM (Yield Analysis Module) to detect hot spots on pre-OPC layouts. Conventional DRC-based search is not able to surpass YAM, as it enables to identify hot spots in either much easier way or even ones that are unable to be found by DRC. We have developed a sophisticated methodology to detect and fix OPC- and/or litho-unfriendly patterns. It is confirmed to enlarge process window and the degree of freedom on OPC work.

Paper Details

Date Published: 1 April 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692513 (1 April 2008); doi: 10.1117/12.772409
Show Author Affiliations
Yeonah Shim, DongbuHiTek (South Korea)
Jaeyoung Choi, DongbuHiTek (South Korea)
Jeahee Kim, DongbuHiTek (South Korea)
Bo Su, Anchor Semiconductor, Inc. (United States)
Ping Zhang, Anchor Semiconductor, Inc. (United States)
Keun-Young Kim, International Technology Alliances, Inc. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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