Share Email Print

Proceedings Paper

Practical and bias-free LWR measurement by CDSEM
Author(s): S.-B. Wang; Y. H. Chiu; H. J. Tao; Y. J. Mii
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The importance of LWR/LER has been wildly treated as an important process parameter to obtain good device performance especially entering 45nm era. The accurate estimation of the metrics is even more important as semiconductor fabrication keeps downsizing. In regular LWR/LER measurement by CDSEM, measurement noise is inevitable and causes bias from true roughness. One early bias-reduction roughness measurement method is by J. Villarrubia and B. Bunday [Proc. SPIE 5752, 480 (2005)] in which multiple images with different frame number are collected and averaged to reduce the noise level after edge position aligned (that is only possible in low noise level). Another proposal by A. Yamaguchi, etc. [Proc. SPIE 6152, 61522D (2006)] is curve fitting with a fixed semi-experimental formula to a measurement curve as a function of the number of scan line of summing. Both methods require complicated image/data collection and calculation method to obtain true roughness. We propose a practical and bias-free roughness measurement method here that is improved version of the two methods, and evaluate noise with multiple measurements at the same line which has adequate scan line summing number so that line edge alignment is doable no matter the noise level. We have verified that the noise is close to Gaussian distribution and the true roughness is estimable for different scan line summing number. The obtained true roughness is also verified by TEM picture. The advantage of this method is practical to commercial CDSEM application in combine with simple offline calculation.

Paper Details

Date Published: 24 March 2008
PDF: 10 pages
Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 692222 (24 March 2008); doi: 10.1117/12.772394
Show Author Affiliations
S.-B. Wang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Y. H. Chiu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
H. J. Tao, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Y. J. Mii, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)

Published in SPIE Proceedings Vol. 6922:
Metrology, Inspection, and Process Control for Microlithography XXII
John A. Allgair; Christopher J. Raymond, Editor(s)

© SPIE. Terms of Use
Back to Top