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Proceedings Paper

Effective learning and feedback to designers through design and wafer inspection integration
Author(s): Crockett Huang; Hermes Liu; S. F. Tzou; Allen Park; Chris Young; Ellis Chang
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Paper Abstract

As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.

Paper Details

Date Published: 4 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692506 (4 March 2008); doi: 10.1117/12.772242
Show Author Affiliations
Crockett Huang, United Microelectronics Corp. (Taiwan)
Hermes Liu, United Microelectronics Corp. (Taiwan)
S. F. Tzou, United Microelectronics Corp. (Taiwan)
Allen Park, KLA-Tencor Corp. (United States)
Chris Young, KLA-Tencor Corp. (United States)
Ellis Chang, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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